زین العابدین نوابی شیرازی
کتابهای تالیفی
- Zainalabedin Navabi Shirazi. "VHDL: Analysis and Modeling of Digital System." : McGraw Hill, 1993.
- Zainalabedin Navabi Shirazi. "VHDL: Analysis and Modeling of Digital System, Second Edition." : McGraw Hill, 1998.
- Zainalabedin Navabi Shirazi. "Verilog Digital system Design." : MC -Graw Hill, 1999.
- Zainalabedin Navabi Shirazi. "Hardware Description in Verilog." : CRC IEEE PRESS, 2000.
- Zainalabedin Navabi Shirazi. "Verilog Computer-Based Training Course." : McGraw Hill, 2002.
- Zainalabedin Navabi Shirazi. "Digital Design and Implementation with Field Programmable Devices." : Kluwer, 2004.
- Zainalabedin Navabi Shirazi. "Verilog Digital System Design (Second Edition)." : McGraw Hill, 2006.
- Zainalabedin Navabi Shirazi. "Embedded Core Design with FPGAs." : McGraw Hill, 2006.
- Zainalabedin Navabi Shirazi. "The VLSI Handbook-Section XIII." : CRC IEEE PRESS, 2006.
- Zainalabedin Navabi Shirazi. "VHDL: Modular Design and Synthesis of Cores and Systems." : McGraw Hill, 2007.
کتاب های غیر از تالیف و ترجمه
مقالات چاپ شده در نشریات بینالمللی
- Zainalabedin Navabi Shirazi. "A Design tool for the analysis of rach pinion stearing systems." INTERNATIONAL JOURNAL OF COMPUTER APPLICATIONS IN TECHNOLOGY -, no. --- (1732): -.
- Zainalabedin Navabi Shirazi. "Design and Description of Hardware Using a Standard Hardware Language." MICROELECTRONICS JOURNAL -, no. --- (1732): -.
- Zainalabedin Navabi Shirazi. "Digitizing for Computer-Aided Finite Element Model Generation - Part 2. Use of Digitizing in Mesh Generation." Journal of Mechanical Design - Transactions of the ASME -, no. --- (1980): 102-560.
- Zainalabedin Navabi Shirazi. "Digitizing for Computer-Aided Finite Element Model Generation—Part 1: The General Program." Journal of Mechanical Design - Transactions of the ASME -, no. 29403 (1980): 105-552.
- Hill F J , Swanson R E , Masud M , and Zainalabedin Navabi Shirazi. "Structure Specification with a Procedural Hardware Desription Language." IEEE TRANSACTIONS ON COMPUTERS C-30, no. 2 (1981): 157-161.
- Zainalabedin Navabi Shirazi, F J Hill , C H Chiang , Duan Ping Chen , and M Masud . "Hardware Compilation from an RTL to a Storage Logic Array Target." IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 3, no. 3 (1984): 208-217.
- Zainalabedin Navabi Shirazi. "Generating Gate Level Two Phase Dynamic MOS Logic From AHPL." Microprocessing and Microprogramming 16, no. 2-3 (1985): 89-94.
- Zainalabedin Navabi Shirazi, and Kia Doroudi . "Compiling an RT Level Hardware Description Language into Layout of NMOS Cells." Microprocessing and Microprogramming 18, no. 1,5 (1986): 123-129
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- Zainalabedin Navabi Shirazi. "User Manual for AHPL Simulator ( HPSIM2 ) / AHPL Compiler ( HPCOM )." Published by Engineering Experiment Station, university of Arizona -, no. --- (1988): -.
- Zainalabedin Navabi Shirazi. "System Test : What Why and How." IEEE DESIGN & TEST OF COMPUTERS -, no. --- (1989): -.
- Zainalabedin Navabi Shirazi. "Faculty Profile Zainalabedin Navabi of N.U.Speaks Language of Computers." Micro News Publication of Massachusetts Microelectronics center 4, no. 2 (1990): -.
- Zainalabedin Navabi Shirazi, and John Spillane . "Synthesis of VLSI Circuits From Behavioral Descriptions." MICROELECTRONICS JOURNAL 22, no. 6 (1991): 13-1.
- Zainalabedin Navabi Shirazi. "User Manual for OCT2HILO Program." Published by massachusetts Microelectronics Center, Wwstboro MA -, no. --- (1991): -.
- Zainalabedin Navabi Shirazi. "Investigating Back - Annotation of High Level Descriptions." The International Journal of Simulation Society of computer Simulation -, no. --- (1991): -.
- Zainalabedin Navabi Shirazi. "Compiling Gate RC Models Into a Top Level Simulation Model for Rough Timing Analysis of VLSI Circuits." MICROPROCESSORS AND MICROSYSTEMS 15, no. 6 (1991): 313-320
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- Zainalabedin Navabi Shirazi, and Kia Doroudi . "HDL Front End for a Cell Based Silicon Compiler." International Journal of Gaming and Computer-Mediated Simulations -, no. --- (1992): -.
- Zainalabedin Navabi Shirazi. "A High Level Language For Design and Modeling of Hardware." Journal of Systems and Software -, no. 9 (1992): -.
- Zainalabedin Navabi Shirazi. "Advanced VHDL for Hardware Design and Modelung." Pubblished by Okura and Company Ltd, Tokyo, Japan -, no. --- (1993): -.
- Zainalabedin Navabi Shirazi. "VHDL for Digital Design and Simulation." Proceedings of SCS International Conference on Simulation in Engineering Education -, no. 25 (1993): 114-119.
- Zainalabedin Navabi Shirazi. "A Transistor Level Link for VHDL Simulation of VLSI Circuits." SIMULATION-TRANSACTIONS OF THE SOCIETY FOR MODELING AND SIMULATION INTERNATIONAL 64, no. --- (1995): 3 185-3197 .
- B Alizadeh , and Zainalabedin Navabi Shirazi. "Word Level Symbolic Simulation in Processor Verification." IET Computers and Digital Techniques 151, no. 5 (2004): 356 - 366.
- Zainalabedin Navabi Shirazi, Shahrzad Mirkhani , Meisam Lavasani , and Fabrizio Lombardi . "Using RT Level Component Descriptions For Single Stuck - at Hierarchical Fault Simulation." JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS 20, no. 6 (2004): 589-575.
- Saeed Shamshiri , Hadi Esmaeilzadeh , and Zainalabedin Navabi Shirazi. "Instruction - Level Test Methodology for CPU Core Self - Testing." ACM Transaction 10, no. 4 (2005): 689-678.
- Ehsan Atoofian , and Zainalabedin Navabi Shirazi. "A Test Approach for Look - Up Table Based FPGAs." JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 21, no. 1 (2006): 141-146.
- Shervin Sharifi , Javid Jaffari , Mohammad Hosseinabady , Ali Afzali Kousha, and Zainalabedin Navabi Shirazi. "Scan - Based Structure with Reduced Static and Dynamic Power Consumption." Journal of Low Power Electronics 2, no. 3 (2006): 477-487.
- Mohammad Hosseinabady , Pejman Lotfi Kamran , and Zainalabedin Navabi Shirazi. "Low Test Application Time Resource Binding for Behavioral Synthesis." ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 2, no. 2 (2007): 1-22.
- Ali Shahabi , Nima Honarmand , Hasan Sahafi , and Zainalabedin Navabi Shirazi. "Degradable mesh-based on-chip networks using programmable routing tables." IEICE Electronics Express 4, no. 10 (2007): 339-332.
- Mohammad Hosseinabady , Pejman Lotfi Kamran , Fabrizio Lombardi , and Zainalabedin Navabi Shirazi. "Low Overhead DFT Using CDFG by Modifying Controller." IET Computers and Digital Techniques 4, no. 1 (2007): 333-322.
- , , Bijan Alizadehmalafeh, and Zainalabedin Navabi Shirazi. "A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits." IEEE DESIGN & TEST OF COMPUTERS 30, no. 4 (2013): 49-59.
- Hossein Sabaghian, Seyed Ali Shahabi, and Zainalabedin Navabi Shirazi. "A Novel Modeling Approach for System-Level Application Mapping Targeted for Configurable Architecture." CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE 37, no. 4 (2014): 192-202.
- Arezoo Kamran, and Zainalabedin Navabi Shirazi. "Hardware Acceleration of Online Error Detection in Many-Core Processors." CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE 38, no. 2 (2015): 143-153.
- Hassan Sohofi, and Zainalabedin Navabi Shirazi. "System-level assertions: approach for electronic system-level verification." IET Computers and Digital Techniques 9, no. 3 (2015): 142-152.
- Samaneh Ghandali, Bijan Alizadehmalafeh, , and Zainalabedin Navabi Shirazi. "Automatic High-level Data-flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition." IEEE TRANSACTIONS ON COMPUTERS 64, no. 6 (2015): 1579-1593.
- Arezoo Kamran, and Zainalabedin Navabi Shirazi. "Self-Healing Many-Core Architecture: Analysis and Evaluation." VLSI Design 2016, no. 1 (2016): 1-17.
- Arezoo Kamran, and Zainalabedin Navabi Shirazi. "Stochastic testing of processing cores in a many-core architecture." INTEGRATION-THE VLSI JOURNAL 55, no. 1 (2016): 183-193.
- Zana Ghaderi, Mohammad Ebrahimi, Eli Bozorgzadeh, Nader Bagherzadeh, and Zainalabedin Navabi Shirazi. "SENSIBLE: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs." IEEE TRANSACTIONS ON COMPUTERS 66, no. 5 (2017): 919-926.
- Fatemeh Refan, Bijan Alizadehmalafeh, and Zainalabedin Navabi Shirazi. "Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 25, no. 7 (2017): 2059-2070.
- Reza Sharafinejad, Bijan Alizadehmalafeh, and Zainalabedin Navabi Shirazi. "Automatic Correction of Dynamic Power Management Architecture in Modern Processors." IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 26, no. 2 (2018): .
- Mohammad Ebrahimi, and Zainalabedin Navabi Shirazi. "Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information." IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 39, no. 10 (2020): .
- Mohammad Ebrahimi, Rezgar Sadeghi, and Zainalabedin Navabi Shirazi. "LUT Input Reordering to Reduce Aging Impact on FPGA LUTs." IEEE TRANSACTIONS ON COMPUTERS 69, no. 10 (2020): 1500-1506.
- محمدرضا بهارانی، حمید نوری، محمد علی عسگری و زین العابدین نوابی شیرازی. "کاوش فضای طراحی سطح بالای مدلهای نوروفازی خطی محلی برای سیستم های نهفته." FUZZY SETS AND SYSTEMS 253، 0 (1393): 44-63.
مقالات چاپ شده در نشریات داخلی
همایشهای بینالمللی
- , , and Zainalabedin Navabi Shirazi. "Designing Optimal Forwarding Tbales with Genetic Algorithm." First ACM SIGCOMM ASIA Workshop 2005, Beijing.
- , and Zainalabedin Navabi Shirazi. "Property Checking based on Hierarchical Integer Equations." ACSD'04, Hamilton.
- , and Zainalabedin Navabi Shirazi. "Using Integer Equations to Check PSL Properties in RT Level Design." IWSOC'04, Banff.
- , , , , , and Zainalabedin Navabi Shirazi. "MCBIST: A New On-Line BIST Scheme." WRTLT'04, Osaka.
- , , , and Zainalabedin Navabi Shirazi. "A Binary Wavelet Test Compression." WRTLT'04, Osaka.
- , , , , , and Zainalabedin Navabi Shirazi. "Interleaved Scan-Cell Architecture for Low Power Test." WRTLT'04, Osaka.
- , , and Zainalabedin Navabi Shirazi. "TEST Instruction Set for High level Self-Testing of CPU Cores." 2004 Asian Test Symposium, Taiwan.
- , , , Zainalabedin Navabi Shirazi, and Ali Afzali Kousha. "Architecture of a Data Compression-based Low-power Scan-path." Proceedings of the 16th International Conference on Microelectronics, Tunis.
- , and Zainalabedin Navabi Shirazi. "An Effective VHDL-AMS Simulation Algorithm with Event Partitioning." VLSI Design 2005, Kalkate.
- , , , , and Zainalabedin Navabi Shirazi. "TED: A Data Structure for Microprocessor Verification." ASP-DAC 2005, Shanghai.
- , , Ali Afzali Kousha, and Zainalabedin Navabi Shirazi. "A New Protocol Stack Model for Network on Chip." ISVLSI 2006, Karlsruhe.
- , Ali Afzali Kousha, and Zainalabedin Navabi Shirazi. "Low-power and low-latency cluster topology for local traffic NoCs." ISCAS 2006, Kos.
- , , , , Ali Afzali Kousha, Omid Fatemi, and Zainalabedin Navabi Shirazi. "Dynamic Routing Algorithm for Avoiding Hot Spots in On-chip Networks." DTIS 2006, Tunis.
- , , Ali Afzali Kousha, Omid Fatemi, and Zainalabedin Navabi Shirazi. "NoC Hot Spot Minimization Using AntNet Dynamic Routing Algorithm." ASAP'06, Colorado.
- Zainalabedin Navabi Shirazi, , and . "The Scalable and Reconfigurable DFT for Embedded A/MS Cores." International SoC Design Conference, Seoul.
- , Ali Afzali Kousha, and Zainalabedin Navabi Shirazi. "A Mesochronous Technique for Communication in Network on Chips." International SoC Design Conference, Seoul.
- Mohammad Riazati, Siamak Mohammadi, and Zainalabedin Navabi Shirazi. "Non-overlapping Set of Efficient Assertions." Norchip Conference,.
- Zainalabedin Navabi Shirazi, , and . "An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing." Asian Test Symposium, Fukuoka.
- Zainalabedin Navabi Shirazi, , and . "ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs." Asian Test Symposium, Fukuoka.
- Mohammad Riazati, Siamak Mohammadi, and Zainalabedin Navabi Shirazi. "Assertion Efficiency Assessment Method." 7th Workshop on RTL and High Level Testing, WRTLT'06, Fukuoka.
- Mohammad Riazati, Siamak Mohammadi, Ali Afzali Kousha, and Zainalabedin Navabi Shirazi. "Improved Assertion Lifetime via Assertion Based Testing Methodology." 18th International Conference on Microelectronics, ICM 2006, Dhahran.
- , , , Saeed Safari, and Zainalabedin Navabi Shirazi. "A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services." DDECS, Krakow.
- , , and Zainalabedin Navabi Shirazi. "Using the Inter- and Intra-Switch Regularity in NoC Switch Testing." DATE-07 Conference, Nice.
- , , , , and Zainalabedin Navabi Shirazi. "High Level Synthesis of Degradable ASICs Using Virtual Binding." VLSI Test Symposium, California.
- , , , and Zainalabedin Navabi Shirazi. "A UML Based System Level Failure Rate Assessment Technique for SoC Designs." VLSI Test Symposium, California.
- , , and Zainalabedin Navabi Shirazi. "Programmable Routing Tables for Degradable Mesh-Based Networks on Chips." ICEE 2007, Tehran.
- , , , Marjan Sirjani, and Zainalabedin Navabi Shirazi. "A New Approach for Design and Verification of Transaction Level Models." IEEE International Symposium on, New Orleans.
- , , and Zainalabedin Navabi Shirazi. "Programmable RoutingTables for Degradable Torus Based Networks on Chip." ISCAS 2007, Louisiana.
- , , Zainalabedin Navabi Shirazi, , , , and . "Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC." International On-Line Testing Symposium, Crete.
- , , and Zainalabedin Navabi Shirazi. "An Analytical Model for Reliability Evaluation of NoC Architectures." International On-Line Testing Symposium, Crete.
- , , , Saeed Safari, and Zainalabedin Navabi Shirazi. "On-Chip Verification of NoCs Using Assertion Processors." DSD 2007, Lübeck.
- Majid Nabi, Hamid Shojaei, Siamak Mohammadi, and Zainalabedin Navabi Shirazi. "Assignment Coverage, A Complementary Coverage Metric in Formal Verification." Design & Technology of Intgrated Systems (DTIS '07), Robat .
- , , and Zainalabedin Navabi Shirazi. "Synthesizable and Improved Performance System Level Design of a Sequential C++ Code Using a Rule Based Technique." EWDTS'07, Yerevan.
- , , and Zainalabedin Navabi Shirazi. "A Heuristic Search Algorithm for Re-routing of On-Chip Networks in the Presence of Faulty Links and Switches." EWDTS'07, Yerevan.
- Zainalabedin Navabi Shirazi, and . "Testing of Routers in NoC Mesh Architecture Using Router's Functionality." EWDTS'07, Yerevan.
- , , and Zainalabedin Navabi Shirazi. "Utilizing ESL Methodology: A Network Processor Case Study." EWDTS'07, Yerevan.
- Mohammad reza Jamali, , , Zainalabedin Navabi Shirazi, and Caro Lucas. "Toward Embedded Emotionally Intelligent System." EWDTS'07, Yerevan.
- , , , and Zainalabedin Navabi Shirazi. "High-level Analysis for Reconfiguration of a Fault Tolerant Mesh-based NoC Architecture Using Transaction Level Modeling." EWDTS'07, Yerevan.
- , and Zainalabedin Navabi Shirazi. "DRA: A Dynamic Reconfiguration Method for Error Recovery of RT Level Designs." EWDTS'07, Yerevan.
- , , , and Zainalabedin Navabi Shirazi. "Processor Description in APDL for Design Space Exploration of Embedded Processors." EWDTS'07, Yerevan.
- , , , and Zainalabedin Navabi Shirazi. "An Exhaustive Test Strategy Based on Flooding Routing for NoC Switch Testing." EWDTS'07, Yerevan.
- , , , and Zainalabedin Navabi Shirazi. "APDL: A Processor Description Language for Design Space Exploration of Embedded Processor." FDL 2007, Barcelona.
- , , , , and Zainalabedin Navabi Shirazi. "A Configurable TLM Model of Avalon Bus for an ESL Design Library." FDL 2007, Barcelona.
- , , , and Zainalabedin Navabi Shirazi. "Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model." DFT 2007, Rome.
- , , , and Zainalabedin Navabi Shirazi. "An HDL-Based Platform for High Level NoC Switch Testing." Asian Test Symposium, Beijing.
- Majid Nabi, Hamid Shojaei, Siamak Mohammadi, and Zainalabedin Navabi Shirazi. "Optimized Assignment Coverage Computation in Formal Verification of Digital Systems." Asian Test Symposium 2007, Beijing.
- , , Mohammad Mirzai, and Zainalabedin Navabi Shirazi. "Enhanced TED: A New Data Structure for RTL Verification." VLSI Design 2008, Hyderabad.
- , , , Ali Afzali Kousha, and Zainalabedin Navabi Shirazi. "Stall Power Reduction in Pipelined Architecture Processors." VLSI Design 2008, Hyderabad.
- , , , , and Zainalabedin Navabi Shirazi. "An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations." VLSI Design, Hyderabad.
- , , , , and Zainalabedin Navabi Shirazi. "A New Structure for Interconnect Offline Testing." EWDTS 2012, Kharkov.
- , , , , and Zainalabedin Navabi Shirazi. "An Improved Scheme for Pre-computed Patterns in Core-based SoC Architecture." EWDTS 2012, Kharkov.
- , , and Zainalabedin Navabi Shirazi. "Extracting Complete Set of Equations to Analyze VHDL-AMS Descriptions." EWDTS 2012, Kharkov.
- , , Behjat Forouzandeh, and Zainalabedin Navabi Shirazi. "Optimization Considerations in QCA Designs." EWDTS 2012, Kharkov.
- , , , and Zainalabedin Navabi Shirazi. "BS 1149.1 Extensions for an Online Interconnect Fault Detection and Recovery." ITC 2012, California.
- , , and Zainalabedin Navabi Shirazi. "An Online Method for Serial Interconnects Testing." WRTLT 2012,.
- Payman Behnam, Hossein Sabaghian, Bijan Alizadehmalafeh, Kamyar Mohajerani, and Zainalabedin Navabi Shirazi. "A Probabilistic Approach for Counterexample Generation to Aid Design Debugging." EWDTS 2013, Rustavi.
- Arezoo Kamran, and Zainalabedin Navabi Shirazi. "Online Periodic Test Mechanism for Homogeneous Many-core Processors." International Conference on Very Large Scale Integration (VLSI-SoC 2013), İSTANBUL.
- , Seyed Ali Shahabi, , and Zainalabedin Navabi Shirazi. "Configurable Systolic Matrix Multiplication." VLSI Design, Mumbai.
- Hassan Sohofi, and Zainalabedin Navabi Shirazi. "Assertion-Based Verification for System-Level Designs." ISQED, سانتاکلارا.
- Payman Behnam, Bijan Alizadehmalafeh, and Zainalabedin Navabi Shirazi. "Automatic Correction of Certain Design Errors Using Mutation Technique." ETS 2014 (European Test Symposium),.
- Marziyeh Mohammadi, Somayeh Sadeghi, Nasser Masoumi, and Zainalabedin Navabi Shirazi. "An Off-line MDSI Interconnect BIST Incorporated in BS 1149.1." ETS 2014 (European Test Symposium),.
- Arezoo Kamran, and Zainalabedin Navabi Shirazi. "Homogeneous Many-core Processor System Test Distribution and Execution Mechanism." ETS 2014 (European Test Symposium),.
- Somayeh Sadeghi, Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi, and Masahiro Fujita. "Improving Polynomial Datapath Debugging with HEDs." ETS 2014 (European Test Symposium),.
- Najmeh Farajipour, and Zainalabedin Navabi Shirazi. "Back-annotation of Gate-level Power Properties into System Level Description." NEWCAS 2014,.
- Farimah Farahmandi, Bijan Alizadehmalafeh, and Zainalabedin Navabi Shirazi. "Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits." ISVLSI 2014, Tampa.
- , , and Zainalabedin Navabi Shirazi. "A Heuristic Path Selection Method For Small Delay Defects Test." DFT 2014, Amsterdam.
- Shahrzad Keshavarz, Amir Reza Nekouei, and Zainalabedin Navabi Shirazi. "Preemptive Multi-bit IJTAG Testing with Reconfigurable Infrastructure." DFT 2014, Amsterdam.
- Samaneh Ghandali, Bijan Alizadehmalafeh, and Zainalabedin Navabi Shirazi. "Low Power Scheduling in High-level Synthesis using Dual-Vth Library." ISQED 2015, سانتاکلارا.
- Mohammad Hashem Haghbayan, Amir Mohammad Rahmani, Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Zainalabedin Navabi Shirazi, and Hannu Tenhunen. "Power-Aware Online Testing of Manycore Systems in the Dark Silicon Era." Design Automation & Test in Europe (DATE 2015),.
- Mehran Goli, Amin Ghasemazar, and Zainalabedin Navabi Shirazi. "Application-Specific Power-Aware Mapping for Reconfigurable NoC Architectures." Design and Technology of Integrated Systems (DTIS2015), Naples.
- Rasoul Jafari, Elham Zahraei Salehi, and Zainalabedin Navabi Shirazi. "Utilizing NOPs for Online Deterministic Testing of Simple Processing Cores." Design and Technology of Integrated Systems (DTIS2015), Naples.
- Amir Reza Nekouei, and Zainalabedin Navabi Shirazi. "Multi-Valued Logic Test Access Mechanism for Test Time and Power Reduction." Design and Technology of Integrated Systems (DTIS2015), Naples.
- Somayeh Sadeghi, Arezoo Kamran, Farnaz Forooghifar, and Zainalabedin Navabi Shirazi. "Aging in Digital Circuits and Age Monitoring: Object-Oriented Modeling and Evaluation." Design and Technology of Integrated Systems (DTIS2015), Naples.
- Somayeh Sadeghi, Mehdi Kamal, John Mcneil, , and Zainalabedin Navabi Shirazi. "Online Self Adjusting Progressive Age Monitoring of Timing Variations." Design and Technology of Integrated Systems (DTIS2015), Naples.
- Fatemeh Refan, Bijan Alizadehmalafeh, and Zainalabedin Navabi Shirazi. "Signature Oriented Model Pruning to Facilitate Multi-Threaded Processors Debugging." IEEE VLSI Test Symposium (VTS 2015), napa valley california.
- Mohammad Ebrahimi, Zana Ghaderi, Eli Bozorgzadeh, and Zainalabedin Navabi Shirazi. "Path Selection and Sensor Insertion Flow for Age Monitoring in FPGAs." Design, Automation & Test in Europe (DATE 2016), Dresden.
- Morteza Soltani, Mohammad Ebrahimi, and Zainalabedin Navabi Shirazi. "Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping." GLSIVLSI 2016, Boston.
- Seyedeh Hanieh Hashemi, and Zainalabedin Navabi Shirazi. "Optimistic Clock Adjustment for preventing Better-Than-Worst-Case Violations." VLSI SoC 2016, Tallinn.
- Hanieh Hashemi, Arash Fouman Ajirlou, Morteza Soltani, and Zainalabedin Navabi Shirazi. "Early Prediction of Timing Critical Instructions in Pipeline Processor." Baltic Electronic Conference (BEC), Tallinn.
- Hamed Najafi haghi, Mikhail Chupilko, Alexander Kamkin, and Zainalabedin Navabi Shirazi. "ESL Design with RTL-Verified Predesigned Abstract Communication Channels." EWDTS 2016, Yerevan.
- Maksim Jenihhin, Alexander Kamkin, Somayyeh Sadeghi, and Zainalabedin Navabi Shirazi. "Universal Mitigation of NBTI-Induced Aging by Design Randomization." EWDTS 2016, Yerevan.
- Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali Kousha, Massoud Pedram, and Zainalabedin Navabi Shirazi. "TruncApp: A Truncation-based Approximate Divider for Energy Efficient DSP Applications." DATE 2017,.
- Rasoul Sharifi, and Zainalabedin Navabi Shirazi. "Online Profiling for Cluster-Specific Variable Rate Refreshing in High-Density DRAM Systems." European Test Symposium (ETS 2017),.
- , Payman Behnam, Bijan Alizadehmalafeh, and Zainalabedin Navabi Shirazi. "Reducing Search Space for Fault Diagnosis: A Probability-based Scoring Approach." ISVLSI 2017, Bochum.
- Farzane Zokaee, Hossein Sabaghian, Vahid Janfaza, Payman Behnam, and Zainalabedin Navabi Shirazi. "A Novel SAT-based ATPG Approach for Transition Delay Faults." IEEE International High Level Design Validation and Test Workshop (HLDVT),.
- Ramin Rezaeizadeh, Somayyeh Sadeghi, and Zainalabedin Navabi Shirazi. "Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture." GLSIVLSI 2018, Chicago.
- Somayeh Sadeghi kohan, Arash Vafaei, and Zainalabedin Navabi Shirazi. "Near-Optimal Node Selection Procedure for Aging Monitor Placement." IOLTS,.
- Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, and Zainalabedin Navabi Shirazi. "Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling." ETS 2019,.
- Mahsa Akhsham, Atefesadat Seyedolhosseini, and Zainalabedin Navabi Shirazi. "Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme." ETS 2019,.
- Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, and Zainalabedin Navabi Shirazi. "An ESL Environment for Modeling Electrical Interconnect Faults." ISVLSI 2019,.
- Samira Ahmadi farsani, Katayoon Basharkhah, Amin Mohaghegh, and Zainalabedin Navabi Shirazi. "From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization." EWDTS 2019, Batumi.
- Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, and Zainalabedin Navabi Shirazi. "An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements." EWDTS 2019, Batumi.
- Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Carna Zivkovic, Christoph Grimm, and Zainalabedin Navabi Shirazi. "Making System Level Test Possible bt a Mixed-mode, Multi-level, Integrated Modeling Environment." EWDTS 2019, Batumi.
- Seyyede Maryam Ghasemy, Maryam Rajabalipanah, Saeideh Sarmadi, and Zainalabedin Navabi Shirazi. "SCOAP-based Directed Random Test Generation for Combinational Circuits." EWDTS 2019, Batumi.
- Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, and Zainalabedin Navabi Shirazi. "ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links." VTS 2020,.
- Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Maryam Rajabalipanah, Maryam Ghasemi, and Zainalabedin Navabi Shirazi. "Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations." DDECS 2020,.
- Mahboobeh Sadeghipour, Mohammad Ali Saber, and Zainalabedin Navabi Shirazi. "DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation." DDECS 2020,.
- Rezgar Sadeghi, and Zainalabedin Navabi Shirazi. "Built-In Predictors for Dynamic Crosstalk Avoidance." ETS 2020,.
- Maryam Rajabalipanah, [] [], Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, and Zainalabedin Navabi Shirazi. "Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator." IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT),.
- Mohammad Reza Naeemi Khaledi, mohammad ebrahimi, and Zainalabedin Navabi Shirazi. "Compensating Detection Latency of FPGA Scrubbers with a Collaborative Functional Hardware Duplication." 2021 IEEE Microelectronics Design & Test Symposium (MDTS),.
- Mohammad Rasoul Roshanshah, Katayoon Basharkhah, and Zainalabedin Navabi Shirazi. "Online Testing of a Row-Stationary Convolution Accelerator." 2021 IEEE European Test Symposium (ETS),.
- Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, and Zainalabedin Navabi Shirazi. "Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester." 2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS),.
- Mahsa Akhsham, and Zainalabedin Navabi Shirazi. "Integrating an Interconnect BIST with Crosstalk Avoidance Hardware." IOLTS 2021,.
- Mahboube Sadghipour rousari, Hanieh Totonchi Asl, and Zainalabedin Navabi Shirazi. "n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator." ISVLSI 2021,.
- Maryam Rajabali Panah, Mahboube Sadghipour rousari, Zahra Jahanpeima, Gianluca Roascio, Paolo Prinetto, and Zainalabedin Navabi Shirazi. "AFTAB: A RISC-V Implementation with Configurable Gateways for Security." EWDTS 2021,.
- Nooshin Nosrati, [] [], Mahboube Sadghipour rousari, and Zainalabedin Navabi Shirazi. "Concurrent Error Detection for LSTM Accelerators." ETS 2022, Barcelona.
- Nooshin Nosrati, Zainalabedin Navabi Shirazi, and Maksim Jenihhin. "Resiliency to Soft-Errors for Embedded Processors Using ML-based Checkers." ETS 2022, Barcelona.
- Mahboube Sadghipour rousari, Ebrahim Nouri, Fatemeh Sheikhshoaei, , and Zainalabedin Navabi Shirazi. "A Secure Canary-Based Hardware Approach Against ROP." ITASEC 2022, Rome.
- Nooshin Nosrati, Maksim Jenihhin, and Zainalabedin Navabi Shirazi. "MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors." IOLTS 2022, Torino.
- Zahra Hojati, and Zainalabedin Navabi Shirazi. "A Low-Cost Combinational Approximate Multiplier." DDECS 2023, Tallinn.
- Nooshin Nosrati, and Zainalabedin Navabi Shirazi. "A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators." DDECS 2023, Tallinn.
- Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad Javad Zare, and Zainalabedin Navabi Shirazi. "Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction." ETS 2023, Venice.
- Zainalabedin Navabi Shirazi. "Hardware Generation From a Synthesis Subset of VHDL." Spring 1990 VHDL Users Group Meting,.
- Zainalabedin Navabi Shirazi. "Influence of VHDL and Other HDLS on Digital System Design Methodologies." Invited KeyNote Speaker CSICC Conference,.
- Zainalabedin Navabi Shirazi. "Design of Digital Electronics systems with VHDL." A One Day Short Course at Johns Hopkins University sponsored by IEEE and IEEE Computer Society,.
- Zainalabedin Navabi Shirazi. "VHDL Modeling For test Applications." Invited by Technical University of Munich,.
- Zainalabedin Navabi Shirazi. "Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models." International Conference on Computer Hardware Description Languages,.
- Zainalabedin Navabi Shirazi. "The Impact of Hardware Description Languages on the Education of Hardware Design." Proceedings of the Eight Biennial University/Government / Industry Microelectronics Symposium,.
- Zainalabedin Navabi Shirazi. "Impact of VHDL on Teaching of Digital Systems." VHDL Methods Workshop,.
- Zainalabedin Navabi Shirazi. "Advanced VHDL for Hardware Design and Modeling." Presented a 3-Day short course for the Okura Company,.
- Zainalabedin Navabi Shirazi. "Investigating Back Annotation of Controlling Machines." VIUF Spring 1992 Conference,.
- Zainalabedin Navabi Shirazi. "VHDL Modeling." Presented a 3-day short course at Viewlogic system inc,.
- Zainalabedin Navabi Shirazi. "VHDL Structural Models for the Implementation of path Sensitization Test Generation." ICEHDL WMC,.
- Zainalabedin Navabi Shirazi. "Digitizing for Computer Aided Finite Element Model Generation." Proceedings of the ASME Fifth Design Automation Conference,.
- Zainalabedin Navabi Shirazi. "Implementing Timed Logic Simulation in VHDL." Proceedings of VIUF Spring 1992 Conference,.
- Zainalabedin Navabi Shirazi. "Timing Compilation of VLSI Circuits for Fast Timing Simulation." Proceedings of the Twentieth Annual Pittsburgh Conference on modeling and Simulation,.
- Zainalabedin Navabi Shirazi. "Gate Levl Simulation and Testing of Technology Independent RTL Hardware Descriptions." Proceedings of the Fifth IASTED International Symposium on Applied Informatics,.
- Zainalabedin Navabi Shirazi. "Using VHDL in Digital System Test." Presented a tutorial in conjunction with VIUF Conference,.
- Zainalabedin Navabi Shirazi. "Synthesis of Testable Controllers." VIUF Spring 1993 Conference,.
- Zainalabedin Navabi Shirazi. "Modeling for Fault Insertation and Parallel Fault Simulation." VIUF Spring 1993 Conference,.
- Zainalabedin Navabi Shirazi. "Analysis and Modeling of Hardware with VHDL." Presented a 3-Day short course for the Hughes Network Systems,.
- Zainalabedin Navabi Shirazi. "Analysis and Design of Digital Systems with VHDL." Presented a two month course at Teradyne,.
- Zainalabedin Navabi Shirazi. "Effect Simulation of AHPL." Proceedings of the Sixteenth Design Automation Conference,.
- Zainalabedin Navabi Shirazi. "Synthesis Subsets of VHDL." Fall 1989 VHDL Users Group Meeting,.
- Zainalabedin Navabi Shirazi. "Configurable VHDL Models for field Programmable Gate Arrays." VIUF Spring 1993 Conference,.
- Zainalabedin Navabi Shirazi. "Implementing A Complete Test Tool Set in VHDL." Proceedings of VIUF , VHDL International Users' Forum IEEE Computer Society,.
- Zainalabedin Navabi Shirazi. "A VHDL Based Test Environment Including Models for Equivalence Fault Collapsing." VIUF 94,.
- Zainalabedin Navabi Shirazi. "VHDL : A Language for Modeling and Design of Digital Circuits." Control and Modeling; Proceedings of the 1990 IASTED International Conference on Control and Modeling ICCM90,.
- Zainalabedin Navabi Shirazi. "Behavioral VHDL Transistor Models." Proceedings of VIUF Spring 1992 Conference,.
- Zainalabedin Navabi Shirazi. "A Fast cycle based approach for synthesizable RT levl vhdl simulation." ICM conference,.
- Zainalabedin Navabi Shirazi. "Impact of VLSI Technology on the Hardware Description Language AHPL." Proceedings of the IEEE International Conference oNn Circuits and Computers,.
- Zainalabedin Navabi Shirazi. "A top down design proce with VHDL :A tutorial view." The frst computer conference : Educaion , Research and Application,.
- Zainalabedin Navabi Shirazi. "Functional Fault Simulation of VHDL Gate Level models." Proceedings of VIUF , VHDL International Users' Forum IEEE Computer Society,.
- Zainalabedin Navabi Shirazi. "Behavioral Level Modeling of Gate Level Loading Effects." International Conference on Computer Hardware Description Languages,.
- Zainalabedin Navabi Shirazi. "Timing Analysis and Simulation of VLSI Components in VHDL." Proceedings of the 1990 International Conference on Computers and Information ICCI 90,.
- Zainalabedin Navabi Shirazi. "Introduction to VHDL." A Three Day Short Course at the Massachusetts Microelectronics Center,.
- Zainalabedin Navabi Shirazi. "Serial Data Compression for 1149.1 Compatible Core Testing." NATW00 Conference Proceedings,.
- Zainalabedin Navabi Shirazi. "Intermediate Format Standardization:Ambiguities Deficiencies Portability issues Documentation and Improvements." HDLCON 2000 Conference Proceedings,.
- Zainalabedin Navabi Shirazi. "Advanced VHDL Modeling." Invited by Technical University of Munich,.
- Zainalabedin Navabi Shirazi. "HDML:Compiled VHDL in XML." VIUF2000,.
- Zainalabedin Navabi Shirazi. "Extending Second Generation AHPL Software to Accommodate AHPL III." Proceedings of the Fourth International Symposium on Computer Hardware Description Languages,.
- Zainalabedin Navabi Shirazi. "Describing Controlling Hardware in VHDL." Proceedings of the 1991 IEEE ASIC Conference and Exhibit,.
- Zainalabedin Navabi Shirazi. "Adapting Differential Fault Simulation for VHDL Implementation." Proceedings of VIUF , VHDL International Users' Forum,.
- Zainalabedin Navabi Shirazi. "Modeling Microprocessors with VHDL." Invited Speaker for the IEEE Sponsored Lecture Series on VHDL,.
- Zainalabedin Navabi Shirazi. "VITAL : Standard for Model Development and Timing Backannotation." Presented a-3 Day short course at Teradyne,.
- Zainalabedin Navabi Shirazi. "Using VHDL Simulation for Finding Critical Timing Paths." ICEE-96,.
- Zainalabedin Navabi Shirazi. "High Level Test Generation From VHDL Behavioral Descriptions." Proceeding VIUF,.
- Zainalabedin Navabi Shirazi. "Introduction to VHDL." Presented a tutorial in conjunction with ICEHDL Conference,.
- Zainalabedin Navabi Shirazi. "Creating an HEL Link for the VLSI CAD Tools." Proceedings of SCS, International Conference on Simulation in Engineering Education,.
- Zainalabedin Navabi Shirazi. "A vhdl test environment including models for equivalence fault collapsing." Proceeding of the vhdl international users forum,.
- Zainalabedin Navabi Shirazi. "An Introduction to ASIC Designers Faults and a Fault Tolerant VHDL Synthesizer." ICEE-96,.
- Zainalabedin Navabi Shirazi. "Modeling Strategy for post Layout Verification." Proceedings of the 1990 IEEE ASIC Seminar,.
- Zainalabedin Navabi Shirazi. "Modeling Logic Functions in VHDL for Timing Simulation." Society of Computer Simulation ( SCS ); Proceedings of the 1990 Summer Simulation Conference,.
- Zainalabedin Navabi Shirazi. "Component Modeling For Reliability Analysis by Simulation." Proceedings of VIUF , VHDL International Users' Forum IEEE Computer Society,.
- Zainalabedin Navabi Shirazi. "Elements of VHDL For Description of Hardware : A Tutorial View." Proceedings of the 1990 IEEE ASIC Seminar,.
- Zainalabedin Navabi Shirazi. "Using VHDL Critical path Tracing Models for Pseudo Random Test Generation." Proceedings of VHDL International Users Forum,.
- Zainalabedin Navabi Shirazi. "An AHPL Compiler Simulator System." Proceedings of the Sixth Texas Conference on Computing systems,.
- Zainalabedin Navabi Shirazi. "Modeling Layout Library Cells in VHDL." Control and Modeling; Proceedings of the 1990 IASTED International Conference on Control and Modeling ICCM90,.
- Zainalabedin Navabi Shirazi. "Tutorial on Use of VHDL for Description of Digital Systems." Proceedings of the 1991 IEEE ASIC Conference and Exhibit,.
- Zainalabedin Navabi Shirazi. "Micro Introduction to VHDL." Invited Speaker for the IEEE Sponsored Lecture Series on VHDL,.
- Zainalabedin Navabi Shirazi. "AIRE/CE:A Revision Towards CAD Tool Integration." ICM00 IEEE Conference on Electronics,.
- Zainalabedin Navabi Shirazi. "Behavioral VHDL Transistor Slope Models." Proceedings of the 1991 IEEE ASIC Conference and Exhibit,.
- Zainalabedin Navabi Shirazi. "Ethernet LAN Modeling with VHDL." Proceedings of the 8th anuual International HDL Conference & Exhibition,.
- Zainalabedin Navabi Shirazi. "An Exercise In Repairing Behavioral Models for Achieving Improved Testing and Verification." Society of Computer Simulation ( SCS ); Proceedings of the 1990 Summer Simulation Conference,.
- Zainalabedin Navabi Shirazi. "VHDL Modeling for Critical path Tracing." ICEHDL WMC,.
- Zainalabedin Navabi Shirazi. "VHDL Modeling for Equivalence Fault Collapsing." Proceedings of VIUF , VHDL International Users' Forum,.
- Zainalabedin Navabi Shirazi. "VLSI Design Automation Using A Hardware Description Language." Proceedings of the Phoenix Conference on Computers and Communications,.
- Zainalabedin Navabi Shirazi. "VHDL Concurrent Simulation of RT Level Components." Proceedings of VIUF , VHDL International Users' Forum,.
- Zainalabedin Navabi Shirazi. "HDL Modeling for Finding Critical Timing paths." Proceedings of VIUF , VHDL International Users' Forum,.
- Zainalabedin Navabi Shirazi. "Innovative Applications of VHDL Modeling Capabilities." Presented a tutorial in Conjunction with fall 1996 VIUF Conference,.
- Zainalabedin Navabi Shirazi. "Modeling for Logic Level Minmax Simulation." Proceedings of VIUF , VHDL International Users' Forum,.
- Zainalabedin Navabi Shirazi. "Templates for Synthesis from VHDL." Proceedings of the 1990 IEEE ASIC Seminar,.
- Zainalabedin Navabi Shirazi. "Modeling Techniques for Simulation Test and Documentation of Digital Components." Proceedings of VIUF , VHDL International Users' Forum,.
- Zainalabedin Navabi Shirazi. "Bist Modeling and Its Application in Design Verification." Proceedings of VHDL International Users' Forum,.
- Zainalabedin Navabi Shirazi. "Implementation Adaptive Random Test Generation in VHDL." Proceedings of VHDL International Users' Forum,.
- Zainalabedin Navabi Shirazi. "Accelerating test Generation by VLSI Hardware Emulation." NATWOO,.
- Zainalabedin Navabi Shirazi. "Self Adjusting Unidirectional Switch Models for Dynamic Load Calculation and Fast Switch Level Simulation." VIUF Spring 1993 Conference,.
- Zainalabedin Navabi Shirazi. "Behavioral State Machine Description For Synthesis." Fall 1990 VHDL Users Group Meeting,.
- Zainalabedin Navabi Shirazi. "Implementation of IEEE Std 1149-1990 in VHDL." Proceedings of VIUF Spring 1992 Conference,.
- Zainalabedin Navabi Shirazi. "VHDL Description Style for CPU-Like Architectures." VHDL Methods Workshop,.
- Zainalabedin Navabi Shirazi. "ALRE /CE:A Revision Towards CAD Tool Integration." Proceedings of the 12th International Conference on Microelectronics,.
- Zainalabedin Navabi Shirazi. "Digital System synthesis with VHDL." Presented a one month course at Teradyne,.
- Zainalabedin Navabi Shirazi. "Storage Logic Array Realization of RTL Descriptions." Proceedings of the Sixth International Symposium on Computer Hardware Description,.
- Zainalabedin Navabi Shirazi. "A Global Approach to Algebraic Factoring Which is Extendable for Utilizing Dont Cares." Proceedings of ICEE-96,.
- Zainalabedin Navabi Shirazi. "Using VHDL Neural Network Model for Automatic Test Generation." Proceedings of Workshop on Modeling,.